Harm Peter Hofstee

Chief architect of the synergistic processor elements in the Cell Broadband Engine, Hofstee is known for his work on the processor behind the Sony PlayStation 3 and the Roadrunner supercomputer that first broke the 1 Petaflop Linpack benchmark.

Born in the Netherlands, Hofstee received his Doctorandus in Theoretical Physics from the University of Groningen, The Netherlands, in 1988. In 1994 he earned his Ph.D. from California Institute of Technology (or Caltech) in Pasadena, California, United States. His thesis (1995) covered "Synchronizing processes". Following that, he spent two years on the faculty of Caltech.

His interests have included VLSI, multicore and heterogeneous microprocessor architecture, security, system design and programming. He joined the IBM Austin Research Laboratory in 1996, where he worked on microprocessors, including the first CMOS microprocessor (i.e., the IBM Rivina) to demonstrate GHz operation (1997). In mid-2000, he joined the team and served as Chief Architect of the synergistic processor elements in the Cell Broadband Engine, known from its use in the Sony PlayStation 3 and the Roadrunner supercomputer that first broke the 1 Petaflop Linpack benchmark.

The team was from Sony, Sony Computer Entertainment, Toshiba, and IBM — an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001. Cell (shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part) is a multi-core microprocessor microarchitecture that combines a general-purpose Power Architecture core of modest performance with streamlined co-processing elements which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.

The first major commercial application of Cell was in Sony's PlayStation 3 game console. Mercury Computer Systems had a dual Cell server, a dual Cell blade configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Exotic features such as the XDR memory subsystem and coherent Element Interconnect Bus (EIB) interconnect appeared to position Cell for future applications in the supercomputing space to exploit the Cell processor's prowess in floating point kernels. Hofstee holds more than 30 issued patents and over 60 patents pending, most of them Cell-related.