Krste Asanović

Leader of the SCALE group, investigating advanced architectures for energy-efficient high-performance computing, Asanović's breakthrough innovations in memory management and parallel processor design are highly influential within the field.

Asanović has served as an Associate Professor at the University of California, Berkeley in the Computer Science Division of the EECS Department, and has also led the Architecture Group at the International Computer Science Institute, holding a joint appointment with the Lawrence Berkeley National Laboratory. He obtained his B.A. in Electrical Engineering and Computer Science from the University of Cambridge in 1987, and his Ph.D. in 1998 from UC-Berkeley. He joined the MIT faculty in 1998.

His main research areas include Computer Architecture, VLSI design, Parallel Programming and Operating System Design. Asanović has been part of the Parallel Computing Laboratory (ParLab) at UC Berkeley, tackling the design and programming of Many-Core architectures. Previously at MIT, he led the SCALE group, investigating advanced architectures for energy-efficient high-performance computing.

The SCALE group developed technologies for future high-performance low-power computing systems. It took a cross-cutting approach, performing research at all system levels from compiler technology and computer architecture down to circuit design. Its application focus was on low-power processors for embedded devices.

The SCALE project developed a new all-purpose programmable computing architecture for future system designs. SCALE provided efficient support for all kinds of parallelism including data, thread, and instruction-level parallelism, and was intended to be competitive with custom ASICs in both performance and power.