Mr. Bob Blainey

A graduate of University of Toronto - University College in 1988 and Athabasca University in 2005, he is an IBM Fellow and the technical architect of the Hardware Acceleration Laboratory in IBM's Software Group. He has been with IBM for over 20 years, with a consistent focus on deep optimization of software for IBM systems. He spent many years working on program transformations for parallelism and for high performance on systems such as IBM Power and System z. More recently, he has had a focus on re-imagining the relationship between software and hardware in the post-scaling world, which includes optimization of IBM systems and software in the short term and the creation of new system structures in the longer term using disruptive technologies. He is recognized for his distinguished record of innovations that synergize hardware and software technologies. He has focused on ensuring not only that software can exploit hardware capabilities optimally, but also that hardware designs evolve to support higher-performing software. His achievements include breakthrough innovation in compiler technology, leadership of IBM's Java technology, and, most recently, his strategic responsibility for next-generation systems in IBM Software Group. His range of expertise in computer architecture, programming language design, and parallel systems enables a holistic approach to software optimization and collaborative processor design that has delivered dramatic improvements in system performance. He holds a U.S. patent for ?Fast conversion of integer to float using table lookup?.