• Jan 1, 1939
    (b.) - ?

Bio/Description

A computer engineer who pioneered pipelining techniques for improving processor throughput in both hardware and software; techniques to which he contributed seminal ideas include simulated annealing, wave pipelining, multiple instruction stream pipelines, decoupled access – execute architecture, and polycyclic scheduling (aka software pipelining). He has served as a technical consultant to industry and government agencies, including the U.S. Army Electronics Command, Honeywell, the Office of Naval Research, Sperry, the Defense Nuclear Agency, General Electric, and Digital Equipment Corporation (DEC). He grew up in the greater Boston area where he saw his first computer on a high school math class field trip and realized that he wanted to enter the field. He worked for a time at Honeywell, Hewlett-Packard, and IBM, where he gained industrial experience in computer architecture and design. He received his B.A. in Mathematics from Harvard University, in 1961; his M.S. degree in Communication Science from the University of Michigan in 1962; and his Ph.D. in Electrical Engineering from the University of Illinois in 1968. He has served as Professor Emeritus in Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor since June 2000 where his research interests include computer architecture, pipelining theory, parallel processing, performance modeling, intelligent caches, and application tuning. In the 70s, he developed the reservation table approach to optimum design and cyclic scheduling of pipelines, designed and implemented an eight-node symmetric multiprocessor (SMP) system in 1976. Symmetric multiprocessing (SMP) involves a symmetric multiprocessor system hardware and software architecture where two or more identical processors connect to a single, shared main memory, have full access to all I/O devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use SMP architecture. He also developed a variety of systematic methods for modeling performance and enhancing systems, including early work on simulated annealing, wave pipelining, multiple instruction stream pipelines, decoupled access-execute architecture, and polycyclic scheduling (aka software pipelining). In computer science, software pipelining is a technique used to optimize loops, in a manner that parallels hardware pipelining. Software pipelining is a type of out-of-order execution, except that the reordering is done by a compiler (or in the case of hand written assembly code, by the programmer) instead of the processor. Some computer architectures have explicit support for software pipelining, notably Intel's IA-64 architecture. From 1968 to 1973 he was Assistant Professor of Electrical Engineering at Stanford University. In 1973 he joined the University of Illinois at Urbana-Champaign as Professor of Electrical and Computer Engineering; a position he held until 1987. From 1984 to1987 he was also the Hardware Design Director of the Cedar Parallel Supercomputer at the University’s Center for Supercomputing Research. In 1988 he became a Professor of Computer Science and Engineering at the University of Michigan. In addition to this position, he was also the Chair of the Department of Electrical Engineering and Computer Science from 1988 until 1990. From 1994 to 1997 he served as the Director for the Center for Parallel Computing and from 1997 to 2000, he was Associate Chair for Computer Science and Engineering. He was elected Fellow of the IEEE (1984) for "contributions to the use of pipeline structures in computer architecture". He is a recipient of numerous awards including, the 1992 IEEE Harry H. Goode Memorial Award for "pivotal seminal contributions to the design, implementation, and performance evaluation of high performance computer systems"; the 1996 Taylor L. Booth Education Award for "contributions to the establishment of computer engineering as an academic discipline and for nurturing many leaders of this field during their formative years in the profession”; and the 2000 IEEE/ACM Eckert-Mauchly Award "for his seminal contributions to the design, implementation, and performance evaluation of high performance pipelines and multiprocessor systems". He has served on Advisory Boards for universities, industry and government agencies, including Northwestern EE Department, Princeton EE Department, Nexgen Microsystems, Cydrome, Ardent, NCR, National Science Foundation, and the University of Southern California.
  • Date of Birth:

    Jan 1, 1939
  • Noted For:

    Designer and implementer of an eight-node symmetric multiprocessor (SMP) system used by most multiprocessor systems today
  • Category of Achievement:

  • More Info: