• unknown (b.)


Chief Scientist and Senior Vice President of Research since 2009 at NVIDIA; an American worldwide technology company based in Santa Clara, California, he is also the Willard R. and Inez Kerr Bell Professor in the Stanford University School of Engineering and past Chairman of the Computer Science Department at Stanford. NVIDIA manufactures graphics processing units (GPUs), as well as system on a chip units (SOCs) for the mobile computing market. NVIDIA Research, the company?s world-class research organization, is chartered with developing the strategic technologies that will help drive the company?s future growth and success. From 1986 to 1997 he taught at the Massachusetts Institute of Technology (MIT) in Cambridge, Massachusetts where he and his group built the J?Machine and the M?Machine; parallel machines emphasizing low overhead synchronization and communication. Prior to that, at Bell Telephone Laboratories he contributed to the design of the BELLMAC32, an early 32-bit microprocessor, and designed the MARS hardware accelerator. Prior to joining NVIDIA, his corporate involvements included various collaborations at Cray Research since 1989 and Internet router work at Avici Systems starting in 1997. He was Chief Technology Officer at Velio Communications from 1999 until its 2003 acquisition by LSI Logic, as well as founder and former Chairman of Stream Processors, Inc. He received his B.S. degree in Electrical Engineering from Virginia Polytechnic Institute and his M.S. degree in Electrical Engineering from Stanford University. He earned his Ph.D. degree in Computer Science from California Institute of Technology (Caltech) in Pasadena, California. While at Caltech, from 1983 to 1986, he designed the MOSSIM Simulation Engine and the Torus Routing Chip which pioneered wormhole routing and virtual-channel flow control. He has developed a number of techniques used in modern interconnection networks including routing-based deadlock avoidance, wormhole routing, link-level retry, virtual channels, global adaptive routing, and high-radix routers. He has developed efficient mechanisms for communication, synchronization, and naming in parallel computers including message-driven computing and fast capability-based addressing. He has developed a number of stream processors starting in 1995 including Imagine, for graphics, signal, and Image processing, and Merrimac, for scientific computing. He received the ACM/SIGARCH Maurice Wilkes Award in 2000; and in 2002, he was elected a Fellow of the Association for Computing Machinery (ACM), as well as Fellow of the Institute of Electrical and Electronics Engineers (IEEE). He received the Seymour Cray Computer Science and Engineering Award in 2004. In 2007 he was elected to the American Academy of Arts and Sciences, and in 2009 the National Academy of Engineering. In addition, he received the 2010 ACM/IEEE Eckert?Mauchly Award for "outstanding contributions to the architecture of interconnection networks and parallel computers." He has published over 200 papers in these areas and is an author of the textbooks "Digital Systems Engineering" with John Poulton, and "Principles and Practices of Interconnection Networks" with Brian Towles. In addition, he has co-authored: with R. Curtis Harting, ?On-Chip Active Messages for Speed, Scalability, and Efficiency?,. IEEE Trans. Parallel Distrib. Syst. 26(2): 507-515 (2015); with Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, ?Scaling the Power Wall: A Path to Exascale? SC 2014: 830-841; with, James D. Balfour, ?Author retrospective for design tradeoffs for tiled CMP on-chip networks?, ICS 25th Anniversary 2014: 77-79; and with George Michelogiannakis, ?Elastic Buffer Flow Control for On-Chip Networks?, IEEE Trans. Computers 62(2): 295-309 (2013). He has been inventor or co-inventor on over 70 granted patents and has several more pending.
  • Noted For:

    Co-builder of the J–Machine and the M–Machine; parallel machines emphasizing low overhead synchronization and communication
  • Category of Achievement:

  • More Info: