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An Associate Professor at the University of California, Berkeley in the Computer Science Division of the EECS Department, he also leads the Architecture Group at the International Computer Science Institute, and holds a joint appointment with the Lawrence Berkeley National Laboratory. He obtained his B.A. in Electrical Engineering and Computer Science from the University of Cambridge in 1987, and his Ph.D. in 1998 from UC-Berkeley. He joined the MIT faculty in 1998. His main research areas are Computer Architecture, VLSI design, Parallel Programming and Operating System Design. He is part of the Parallel Computing Laboratory (ParLab) at UC Berkeley, tackling the design and programming of Many-Core architectures. Previously at MIT, he led the SCALE group, investigating advanced architectures for energy-efficient high-performance computing. The SCALE group is developing technologies for future high-performance low-power computing systems. It takes a cross-cutting approach, performing research at all system levels from compiler technology and computer architecture down to circuit design. Its recent application focus has been low-power processors for embedded devices. The SCALE project is developing a new all-purpose programmable computing architecture for future system designs. SCALE provides efficient support for all kinds of parallelism including data, thread, and instruction-level parallelism, and is intended to be competitive with custom ASICs in both performance and power.
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    Led the SCALE group, investigating advanced architectures for energy-efficient high-performance computing - his breakthrough innovations in memory management and in parallel processor design are highly influential within the field
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