• 1900
    (b.) - ?


Steve Keckler joined NVIDIA in December 2009 and leads the Architecture Research Group. He is also Professor of both Computer Science and Electrical and Computer Engineering at the University of Texas at Austin, where he has served on the faculty since 1998. His research team at UT-Austin developed scalable parallel processor and memory system architectures, including non-uniform cache architectures; explicit data graph execution processors, which merge dataflow execution with sequential memory semantics; and micro-interconnection networks to implement distributed processor protocols. All of these technologies were demonstrated in the TRIPS experimental computer system. Keckler was previously at the Massachusetts Institute of Technology from 1990 to 1998, where he led the development of the M-Machine experimental parallel computer system. He is an Alfred P. Sloan Research Fellow and a recipient of the NSF CAREER award, the ACM Grace Murray Hopper award, the President's Associates Teaching Excellence Award at UT-Austin, and the Edith and Peter O?Donnell award for Engineering. He earned a BS in Electrical Engineering from Stanford University and an MS and a Ph.D. in Computer Science from the Massachusetts Institute of Technology.
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    Development in scalable parallel processor and memory system architectures
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